#ifndef __EOCV100_H__
#define __EOCV100_H__

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>

static inline uint32_t readl(uint32_t addr)
{	return *(volatile uint32_t *)addr;	}

static inline void writel(uint32_t val, uint32_t addr)
{	*(volatile uint32_t *)addr = val;	}

/* -------------------------  Interrupt Number Definition  ------------------------ */

enum irq_id {
/* --------------------  RISC-V Processor Exceptions Numbers  ------------------- */
//	NMI_EXPn                      = -2,   /* NMI Exception */
//	User_Software_IRQn            = 0U,   /* User software interrupt */
//	Supervisor_Software_IRQn      = 1U,   /* Supervisor software interrupt */
	Machine_Software_IRQn         = 3U,   /* Machine software interrupt */
	User_Timer_IRQn               = 4U,   /* User timer interrupt */
	Supervisor_Timer_IRQn         = 5U,   /* Supervisor timer interrupt */
	Machine_Timer_IRQn            = 7U,   /* Machine Timer Interrupt */
//	Supervisor_External_IRQn      = 9U,   /* Supervisor external interrupt */
	Machine_External_IRQn         = 11U,  /* Machine external interrupt */

/* ---------------------  EOCV100 Specific Interrupt Numbers  ------------------ */	
	RTC_IRQn                      = 16U,  /* RTC interrupt */
	WDT0_IRQn,                            /* WDT0 interrupt */
	WDT1_IRQn,                            /* WDT1 interrupt */
	TIMER0_IRQn,                          /* TIMER0 interrupt */
	TIMER1_IRQn                   = 20U,  /* TIMER1 interrupt */
	TIMER2_IRQn,                          /* TIMER2 interrupt */
	TIMER3_IRQn,                          /* TIMER3 interrupt */
	TIMER4_IRQn,                          /* TIMER4 interrupt */
	TIMER5_IRQn,                          /* TIMER5 interrupt */
	DMA_CH0_IRQn,                         /* DMA Channel 0 interrupt */
	DMA_CH1_IRQn,                         /* DMA Channel 1 interrupt */
	DMA_CH2_IRQn,                         /* DMA Channel 2 interrupt */
	DMA_CH3_IRQn,                         /* DMA Channel 3 interrupt */
	DMA_CH4_IRQn,                         /* DMA Channel 4 interrupt */
	DMA_CH5_IRQn                  = 30U,  /* DMA Channel 5 interrupt */
	DMA_CH6_IRQn,                         /* DMA Channel 6 interrupt */
	DMA_CH7_IRQn,                         /* DMA Channel 7 interrupt */
	SPI0_IRQn,                            /* SPI0 interrupt */
	SPI1_IRQn,                            /* SPI1 interrupt */
	SPI2_IRQn,                            /* SPI2 interrupt */
	SPI3_IRQn,                            /* SPI3 interrupt */
	I2C0_IRQn,                            /* I2C0 interrupt */
	I2C1_IRQn,                            /* I2C1 interrupt */
	UART0_IRQn,                           /* UART0 interrupt */
	UART1_IRQn                    = 40U,  /* UART1 interrupt */
	UART2_IRQn,                           /* UART2 interrupt */
	UART3_IRQn,                           /* UART3 interrupt */
	UART4_IRQn,                           /* UART4 interrupt */
	S0_ECC_ERR_1BIT_IRQn,                 /* LMU S0_ECC_ERR_1BIT interrupt */
	S0_ECC_ERR_XBIT_IRQn,                 /* LMU S0_ECC_ERR_xBIT interrupt */
	S1_ECC_ERR_1BIT_IRQn,                 /* LMU S1_ECC_ERR_1BIT interrupt */
	S1_ECC_ERR_XBIT_IRQn,                 /* LMU S1_ECC_ERR_xBIT interrupt */
	GPIO_IRQn,                            /* GPIO interrupt */
	GPIO_AUX_PORTA0_IRQn,                 /* GPIO_AUX_PORTA0 interrupt */
	GPIO_AUX_PORTA1_IRQn          = 50U,  /* GPIO_AUX_PORTA1 interrupt */
	GPIO_AUX_PORTA2_IRQn,                 /* GPIO_AUX_PORTA2 interrupt */
	GPIO_AUX_PORTA3_IRQn,                 /* GPIO_AUX_PORTA3 interrupt */
	GPIO_AUX_PORTA4_IRQn,                 /* GPIO_AUX_PORTA4 interrupt */
	GPIO_AUX_PORTA5_IRQn,                 /* GPIO_AUX_PORTA5 interrupt */
	GPIO_AUX_PORTA6_IRQn,                 /* GPIO_AUX_PORTA6 interrupt */
	GPIO_AUX_PORTA7_IRQn,                 /* GPIO_AUX_PORTA7 interrupt */
	GPIO_AUX_PORTA8_IRQn,                 /* GPIO_AUX_PORTA8 interrupt */
	GPIO_AUX_PORTA9_IRQn,                 /* GPIO_AUX_PORTA9 interrupt */
	GPIO_AUX_PORTA10_IRQn,                /* GPIO_AUX_PORTA10 interrupt */
	GPIO_AUX_PORTA11_IRQn         = 60U,  /* GPIO_AUX_PORTA11 interrupt */
	GPIO_AUX_PORTA12_IRQn,                /* GPIO_AUX_PORTA12 interrupt */
	GPIO_AUX_PORTA13_IRQn,                /* GPIO_AUX_PORTA13 interrupt */
	GPIO_AUX_PORTA14_IRQn,                /* GPIO_AUX_PORTA14 interrupt */
	GPIO_AUX_PORTA15_IRQn,                /* GPIO_AUX_PORTA15 interrupt */
	GPIO_AUX_PORTA16_IRQn,                /* GPIO_AUX_PORTA16 interrupt */
	GPIO_AUX_PORTA17_IRQn,                /* GPIO_AUX_PORTA17 interrupt */
	GPIO_AUX_PORTA18_IRQn,                /* GPIO_AUX_PORTA18 interrupt */
	GPIO_AUX_PORTA19_IRQn,                /* GPIO_AUX_PORTA19 interrupt */
	GPIO_AUX_PORTA20_IRQn,                /* GPIO_AUX_PORTA20 interrupt */
	GPIO_AUX_PORTA21_IRQn         = 70U,  /* GPIO_AUX_PORTA21 interrupt */
	GPIO_AUX_PORTA22_IRQn,                /* GPIO_AUX_PORTA22 interrupt */
	GPIO_AUX_PORTA23_IRQn,                /* GPIO_AUX_PORTA23 interrupt */
	PWM_STATUS0_IRQn,                     /* PWM_STATUS0 interrupt */
	PWM_STATUS1_IRQn,                     /* PWM_STATUS1 interrupt */
	PWM_FAULT_IRQn,                       /* PWM_FAULT interrupt */
	E_RELAY_STATUS_IRQn,                  /* E_RELAY_STATUS interrupt */
	INT_SARADC_IRQn,                      /* SAR_ADC interrupt */
	INT_I_OVF_IRQn,                       /* METER I_OVF interrupt */
	INT_SC_IA_IRQn,                       /* METER SC_IA interrupt */
	INT_SC_IB_IRQn                = 80U,  /* METER SC_IB interrupt */
	INT_SC_IC_IRQn,                       /* METER SC_IC interrupt */
	INT_U_ALARM_IRQn,                     /* METER U_ALARM interrupt */
	INT_ZC_IRQn,                          /* METER ZC interrupt */
	INT_NLOAD_IRQn,                       /* METER NLOAD interrupt */
	INT_NEG_EX_OVF_IRQn,                  /* METER NEG_EX_OVF interrupt */
	INT_POS_EX_OVF_IRQn,                  /* METER POS_EX_OVF interrupt */
	INT_SINGLE_DONE_IRQn,                 /* MONITOR SINGLE_DONE interrupt */
	INT_CONT_PINGDONE_IRQn,               /* MONITOR CONT_PINGDONE interrupt */
	INT_CONT_PANGDONE_IRQn,               /* MONITOR CONT_PANGDONE interrupt */
	INT_ZCP_PINGDONE_IRQn         = 90U,  /* MONITOR ZCP_PINGDONE interrupt */
	INT_ZCP_PANGDONE_IRQn,                /* MONITOR ZCP_PANGDONE interrupt */
	INT_ZCP_PINGABORT_IRQn,               /* MONITOR ZCP_PINGABORT interrupt */
	INT_ZCP_PANGABORT_IRQn,               /* MONITOR ZCP_PANGABORT interrupt */
	INT_ABN_DONE_IRQn,                    /* MONITOR ABN_DONE interrupt */
	INT_AHB_TIMEOUT_IRQn,                 /* MONITOR AHB_TIMEOUT interrupt */
	INT_AHB_HRESP_ERR_IRQn,               /* MONITOR AHB_HRESP_ERR interrupt */
	INT_ARC_IA,                           /* MONITOR INT_ARC_IA interrupt */
	INT_ARC_IB,                           /* MONITOR INT_ARC_IB interrupt */
	INT_ARC_IC,                           /* MONITOR INT_ARC_IC interrupt */
	INT_PVT_FALL                  = 100U, /* PMU INT_PVT_FALL interrupt */
	INT_PVT_RISE,                         /* PMU INT_PVT_RISE interrupt */

	MAXIMUM_CLIC_IRQn,
};

/* ================================================================================ */
/* ================      Processor and Core Peripheral Section     ================ */
/* ================================================================================ */




typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;


#ifndef BIT
#define BIT(x)		(1UL<<x)
#endif

/* ================================================================================ */
/* ================              Peripheral memory map             ================ */
/* ================================================================================ */
/**
 * SYSMem
 */
/* DMEM base address */
#define MEM_MAP_DMEM_BASE_ADDR                 (0x00200000UL)
/* IMEM base address */
#define MEM_MAP_IMEM_BASE_ADDR                 (0x00400000UL)
/* ROM base address */
#define MEM_MAP_ROM_BASE_ADDR                  (0x00480000UL)
/* FLASH base address */
#define MEM_MAP_FLASH_BASE_ADDR                (0x00500000UL)

/**
 * SUBSYS_CFG
 */
/* Secure engine data */
#define MEM_MAP_SEC_DATA_BASE_ADDR             (0x10000000UL)
/* Secure engine cfg */
#define MEM_MAP_SEC_CFG_BASE_ADDR              (0x10002000UL)
/* DMAC cfg */
#define MEM_MAP_DMAC_BASE_ADDR                 (0x10004000UL)
/* RTC cfg */
#define MEM_MAP_RTC_BASE_ADDR                  (0x10006000UL)
/* PMU base address */
#define MEM_MAP_PMU_BASE_ADDR                  (0x10007000UL)

/**
 * PERI_CFG Per0
 */
/* CRG cfg */
#define MEM_MAP_CRG_BASE_ADDR                  (0x10100000UL)
/* PCL cfg */
#define MEM_MAP_PCL_BASE_ADDR                  (0x10101000UL)
/* GPIO base address */
#define MEM_MAP_GPIO_BASE_ADDR                 (0x10102000UL)
/* TOPSC base address */
#define MEM_MAP_TOPSC_BASE_ADDR                (0x10103000UL)
/* Tsensor base address */
#define MEM_MAP_TSENSOR_BASE_ADDR              (0x10104000UL)

/**
 * PERI_CFG Per1
 */
/* System counter cfg */
#define MEM_MAP_SYSCNT_BASE_ADDR               (0x10110000UL)
/* Timer cfg */
#define MEM_MAP_TIMER_BASE_ADDR                (0x10111000UL)
/* WDT0 cfg */
#define MEM_MAP_WDT0_BASE_ADDR                 (0x10112000UL)
/* WDT1 cfg */
#define MEM_MAP_WDT1_BASE_ADDR                 (0x10113000UL)

/**
 * PERI_CFG Per2
 */
/* UART0 base address */
#define MEM_MAP_UART0_BASE_ADDR                (0x10120000UL)
/* UART1 base address */
#define MEM_MAP_UART1_BASE_ADDR                (0x10121000UL)
/* UART2 base address */
#define MEM_MAP_UART2_BASE_ADDR                (0x10122000UL)
/* UART3 base address */
#define MEM_MAP_UART3_BASE_ADDR                (0x10123000UL)
/* UART4 base address */
#define MEM_MAP_UART4_BASE_ADDR                (0x10124000UL)
/* I2C0 base address */
#define MEM_MAP_I2C0_BASE_ADDR                 (0x10125000UL)
/* I2C1 base address */
#define MEM_MAP_I2C1_BASE_ADDR                 (0x10126000UL)
/* SPI0 cfg */
#define MEM_MAP_SPI0_BASE_ADDR                 (0x10127000UL)
/* SPI1 cfg */
#define MEM_MAP_SPI1_BASE_ADDR                 (0x10128000UL)
/* SPI2 cfg */
#define MEM_MAP_SPI2_BASE_ADDR                 (0x10129000UL)
/* SPI3 cfg, XIP flash */
#define MEM_MAP_SPI3_BASE_ADDR                 (0x1012A000UL)

/**
 * MM
 */
/* Monitor cfg */
#define MEM_MAP_MONITOR_BASE_ADDR              (0x10200000UL)
/* Meter cfg */
#define MEM_MAP_METER_BASE_ADDR                (0x10202000UL)

/*Saradc cfg*/
#define MEM_MAP_SARADC_BASE_ADDR               (0x10203800UL)
/*Sdadc cfg*/
#define MEM_MAP_SDADC_BASE_ADDR                (0x10203C00UL)

/**
 * RCPU
 */
/* TCIP cfg */
#define MEM_MAP_TCIP_BASE_ADDR                 (0xE0000000UL)





//#include <core.h>


#ifdef __cplusplus
}
#endif

#endif

